1. Field of the Invention
The present invention relates to integrated circuit memory devices and, in particular, to an electrically-erasable programmable read only memory (EEPROM) storage cell that utilizes a split floating gate to provide a linear relationship between the number of read pulses applied to the floating gate and the cell's threshold voltage V.sub.T shift.
2. Discussion of the Prior Art
The fundamental challenge in creating an EEPROM cell is to use a controllable and reproducible electrical effect which has enough nonlinearity so that the cell can be written or erased at one voltage in less than 1 ms and can be read at another voltage, without any change in the programmed data for more than 10 years. Fowler-Nordheim tunneling, which was first described by Fowler and Nordheim in 1928, exhibits the required nonlinearity and has been widely used in EEPROM memories.
In silicon, the energy difference between the conduction band and the valence band is 1.1 eV. In silicon dioxide, the energy difference between these bands is about 8.1 eV, with the conduction band in silicon dioxide 3.2 eV above that in silicon. Since electron energy is about 0.025 eV at thermal room temperature, the probability that an electron in silicon can gain enough thermal energy to surmount the Si-to-SiO.sub.2 barrier and enter the conduction band in silicon dioxide is very small. If electrons are placed on a polysilicon floating gate surrounded by silicon dioxide, then this band diagram will by itself insure the retention of data.
Fowler-Nordheim emission, which was observed early in this century for the case of electron emission from metals into vacuums, was also observed by Lenzliger and Snow in 1969 for electron emission from silicon to silicon dioxide. In the presence of a high electric field at the Si--SiO.sub.2 interface, the energy bands will be distorted and there is a small probability that an electron in the conduction band of the silicon will quantum mechanically tunnel through the energy barrier and emerge in the conduction band of the silicon dioxide.
The tunneling current increases exponentially with the applied field in accordance with the following general current density expression: EQU J=(AE2) exp (-B/E)
where
A and B are constants, and PA0 E is the field at the Si--SiO.sub.2 interface
This current is observable at a current density of 10E-6 A/cm2 when the field at the Si--SiO.sub.2 interface is about 10 MV/cm. Local fields of this magnitude, at voltages that are practical for use in microelectronics, can be obtained by applying a voltage across either a thin (about 100.ANG.) oxide grown on bulk silicon or across thicker (about 500.ANG.) oxide grown on polysilicon.
The theoretically ideal EEPROM memory cell comprises a single transistor addressable by applying electrical signals to a specified row and a specified column of the memory array matrix. For example, to write a logic "1" or a logic "0" into this "ideal" cell, a voltage is applied to the control gate corresponding to the row (word line) of the selected cell while a voltage corresponding to either a "1" or a "0" is applied to the source or drain corresponding to the column (bit line) of the selected cell.
The basic concept of the well-known FLOTOX EEPROM memory cell is shown in FIG. 1. In the FLOTOX cell, the tunnel oxide, which typically is less than 100.ANG. thick, is grown over an area defined photolithographically in the drain region (or an extension of the drain region, called buried n+). Charging of the floating gate to program the cell is achieved by grounding the source and the drain and applying a high voltage to the control gate.
The FLOTOX cell is designed such that a large fraction of the applied voltage is coupled across the tunnel oxide resulting in the transport of electrons from the drain to floating gate. Discharge of the floating gate to erase the cell is achieved by grounding the control gate, floating the source and applying a high voltage to the drain. In this case, most of the applied voltage is coupled across the tunnel oxide, but the field is reversed, resulting in tunneling of electrons from the floating gate to the drain. The source is floated so that there is no continuous current path, an important factor when an internal charge pump is used to generate the high voltage from a .ltoreq.5V supply.
If a single transistor memory cell is placed in a typical array with drains connected to metal columns and gates connected to common polysilicon word lines, the erasing of the cell, with the word line grounded, will mean that high voltage is applied to all drains in a common column. Erasing can be inhibited in non-selected cells by taking unselected word lines to a high voltage. However, this means that unselected cells along the same word line may be programmed. To avoid such disturb conditions, as shown in FIG. 1, the FLOTOX cell utilizes a distinct access transistor to isolate the drain from the column bit line. The access transistor is off for rows that are not selected.
FIG. 2 provides a layout of the FIG. 1 FLOTOX cell, with the FIG. 1 cross-section being taken perpendicular to the word line (control gate) and through the tunnel oxide window.
In the conventional FLOTOX EEPROM cell, the buildup of floating gate potential due to electrons arriving from the conduction band of the tunnel oxide affects Fowler-Nordheim tunneling. This relationship is not linear. Therefore, it is difficult to use the standard FLOTOX EEPROM cell in applications that require linearity, such as for example, as an analog weight in a neural network device.
As is well-known, and as shown in FIG. 3, each of the information processing nodes of a neural network has n simultaneous inputs X.sub.i =1, 2, . . . , n, and a threshold quantity .theta..sub.j, which are combined according to Eq (1) to produce single quantity r.sub.j ; ##EQU1##
This is followed by a nonlinear transformation, Eq. (2), which produces the output y.sub.j ; EQU Y.sub.j =.phi.(r.sub.j) (2)
The weighted output of one node can then become one of the inputs to a different node. Thus, the connection of external inputs and nodes by means of information weight parameters W.sub.ij forms a neural network. A connection between node i and node j is a distinct machine component which constrains information flow via the connecting weighting parameter W.sub.ij, as shown in FIG. 4, the numerical value of which is problem-dependent.
The values of the weighting factors W.sub.ij are, thus, the memory of the neural network and must "learn" according to an algorithm specified for establishing the weighting factor. That is, the weight factors must be "trainable".
In utilizing a conventional FLOTOX EEPROM cell for storing the weighting factor, adjustment of the weighting factor involves reading the cell and then adjusting its programming voltage Vpp in response to the associated weighting algorithm. Therefore, the array architecture must provide for a variation in the programming voltage Vpp. However, if the programming voltage Vpp becomes to high, then cell breakdown becomes a problem.
It would, therefore, be desirable to have available an EEPROM cell that relies on a fixed programming voltage Vpp but that can accommodate variations in floating gate voltage V.sub.FG.